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A68 AD62 Address/Data 62 A69 GND Ground A70 AD60 Address/Data 60 A71 AD58 Address/Data 58 A72 GND Ground A73 AD56 Address/Data 56 A74 AD54 Address/Data 54 A75.3V Signal Rail V I/O (5 V.3 V) A76 AD52 Address/Data 52 A77 AD50 Address/Data.Data phases may repeat indefinitely, but are limited by a timer that defines the maximum amount of time that the PCI device may control the bus.This allows main memory to be updated, saving a cache write-back cycle.